Samsung Electronics has announced that it has started initial chip production at its 3nm process node, which uses a gate-all-around (GAA) transistor architecture. Samsung's first implementation of GAA Technology Multi-Bridge C-Channel FETs (MBCFETs) breaks through the performance limitations of FinFETs, improving power efficiency by reducing supply voltage levels while improving performance by increasing drive current capability, said the South Korean technology company.

Samsung said it is starting to use nanosheet transistors alongside semiconductor chips for high-performance, low-power computing applications, with plans to expand into mobile processors.

“Samsung is growing rapidly as we continue to demonstrate leadership in bringing next-generation technologies to manufacturing, such as the foundry industry’s first high-K metal gate, FinFET, and EUV. The 3nm process continues to maintain this leadership with MBCFET," said Siyoung Choi, president and head of foundry business at Samsung Electronics. "We will continue to innovate aggressively in competitive technology development and establish processes that help accelerate technology maturity."

Samsung's proprietary technology utilizes nanosheets with wider channels, enabling higher performance and higher energy efficiency than GAA technology using nanowires with narrower channels. Using 3 nm GAA technology, Samsung will be able to adjust the channel width of the nanosheets to optimize power consumption and performance to meet various customer needs.

In addition, the design flexibility of GAA is very beneficial for Design Technology Co-Optimization (DTCO), which can help improve power, performance, area (PPA) advantages. Compared with the 5nm process, the first-generation 3nm process can reduce power consumption by up to 45%, improve performance by 23%, and reduce the area by 16%, while the second-generation 3nm process is designed to reduce power consumption by up to 50%. , the performance is increased by 30%, and the area is reduced by 35%.