As manufacturing technologies become more complex, so do development, research and development times. No more seeing TSMC and other foundries pop up with new nodes every two years. For the most advanced N3 process, the introduction time of TSMC has been extended to about 2.5 years, and the N2 process has been extended to 3 years.

The extended introduction schedule means that TSMC needs to provide an enhanced version of the N3 node to meet customer needs, as customers continue to improve performance per watt and transistor density. Another reason is that the N2 node relies on a nanosheet structure to achieve a new gate-around field effect transistor (GAA FET), which increases cost and requires new design methods, new IP and other changes. While advanced chip developers will soon move to the N2 process, TSMC's regular customers continue to use various N3 process technologies.

The TSMC Technology Symposium also talked about four N3 node extension processes that will be launched in a few years, bringing the N3 node to a total of five processes N3, N3E, N3P, N3S and N3X. The N3 extension process is an improved technology for ultra-high performance applications, with higher performance count transistor densities, and higher boost voltages. All technologies support the FinFlex architecture, TSMC's secret sauce, maximizing design flexibility and allowing chip designers to precisely optimize performance, power consumption and cost.

N3 and N3E: On the track to mass production

TSMC's first 3-nanometer node, called N3, is expected to be mass-produced in the second half of the year, and physical products will be delivered to customers in early 2023. Primarily aimed at early adopters, they can invest in leading-edge designs and benefit from the performance, power, area (PPA) benefits of advanced nodes. However, it is tailored for a specific type of application, so the N3 node has a narrow application and may not be suitable for all applications.

This gives the N3E process room to play a role, improving performance and reducing power consumption, and increasing applicability in order to increase yield. What needs to be considered is that the logic density is slightly lower. Compared with the N5 process, the N3E transistor density is increased by 1.6 times, and the power consumption is reduced by 34% under the same computing speed and complexity, or the performance is improved by 18% under the same power and complexity. According to TSMC data, N3E is faster than N4X, but supports ultra-high drive current and voltage above 1.2V. Although it has better performance, it has higher power consumption.

The risk trial production of N3E process chips will start in the second or third quarter, and mass production will begin in mid-2023. Commercial N3E process chips will be available in late 2023 or early 2024.

N3P, N3S, and N3X: Performance/Density Improvements

The N3 node extension is not limited to N3E. In 2024, the N3P process will be launched, which is a performance-enhanced version of the N3 process. There is also N3S, which is an enhanced transistor density version of the N3 process. TSMC has not disclosed what has changed or improved compared to the N3 process. The development blueprint does not even have the N3S process, so the performance cannot be confirmed.

For customers who require ultra-high performance in both power consumption and cost, TSMC provides the N3X process. The N3X process is the successor of the N4X process, but also did not disclose detailed information, only that the N3X process supports high driving current and voltage, and the market speculates that the N3X can use the back power supply. At present, we are talking about the process node of FinFET technology. TSMC expects that the N2 node will use the nano-chip structure GAAFET technology to achieve backside power supply. It is uncertain whether the market speculation can be achieved. However, the N3X process improves voltage and performance, and TSMC will have many advantages by then.

FinFlex: N3 Process Secret Weapon

When it comes to enhancing performance, we cannot fail to mention FinFlex technology, the secret weapon of TSMC's N3 process. Simply put, FinFlex allows chip designers to precisely design structural modules for higher performance, higher density and lower power consumption. TSMC's FinFlex technology allows chip designers to mix and match various types of FinFETs within a module to precisely define performance, power consumption and die area. For complex structures such as CPU cores, optimization has many opportunities to improve core performance, while also optimizing the die size of the chip.

While FinFlex technology does not replace performance, density, and voltage changes after node upgrades, FinFlex appears to be a good way to optimize performance, power, and cost. TSMC's N3 node process will bring FinFET technology closer to GAAFET flexibility with nanosheets through FinFlex, including providing adjustable channel width for higher performance or lower power consumption.

In conclusion, like the N7 and N5 nodes, the N3 will be another persistent node series from TSMC. In particular, TSMC's 2nm node is turning to nanosheet GAAFET technology, and the 3nm node series will be the last series of classic advanced FinFET technology, and many customers will use it for a few years or more. This, in turn, is why TSMC prepares multiple versions of the N3 process family and FinFlex technology for different applications, providing more flexibility for chip designers.

N2: mass production in 2025

At the 2022 Technology Forum, TSMC launched the next-generation advanced process N2 for the first time. This technology represents another significant advancement of N3. The speed is increased by 10-15% at the same power, or the power is reduced by 25-30% at the same speed. Usher in a new era of efficient performance.

TSMC N2 technology will use a nanosheet transistor architecture to provide full-node improvements in performance and power efficiency to support next-generation product innovation for TSMC customers. In addition to the mobile computing benchmark version, the N2 technology platform includes a high-performance version, as well as a comprehensive chiplet integration solution. The N2 is scheduled to start production in 2025.