At the 2022 International VLSI Technology Symposium held in April, Babak Sabi, Intel's senior vice president and general manager of the Packaging/Test Development Division, as an engineering expert and industry leader, explained what the advanced packaging ecosystem has encountered. challenges, and take Intel's solutions as an example to illustrate the current and future direction of promotion, but also to drive the standardization of the entire industry to meet future computing needs.

Babak Sabi said that with the growth of computing demands in the digital age, with more and more processor cores and more powerful performance, a key question will gradually come to the table: how to provide sufficient data throughput to maintain high performance , High-output operation result? Big data further generates the demand for high-bandwidth and large-capacity memory, but in reality, the power consumption required for transmission cannot be increased arbitrarily, and a large amount of data needs to be transmitted in an efficient manner.

Babak Sabi pointed out that the cache memory inside the processor core is a static memory (SRAM) structure, and the storage unit usually requires 6 transistors and enjoys almost the same speed as the core. If the cache memory is increased , it is very energy-intensive and requires a lot of silicon wafer area.

He went on to say that the system memory outside the processor package is a dynamic random access memory (DRAM) structure, which requires only one transistor and one capacitor to store a single cell. Speed ??is not easy.

Between the two, HBM (High Bandwidth Memory) stacks multiple dies with TSV (Through-Silicon Via), and a single package uses a 1024bit bus width to provide more space and Higher bandwidth, but requires higher density, more advanced packaging techniques to pack the HBM as close to the processor as possible.

In order to pursue reducing the power consumption per unit of movement and continue to promote interconnection bandwidth and density, Babak Sabi said, not only requires comprehensive innovation in advanced packaging, but also requires the cooperation of the entire industry ecosystem, from system, Circuit boards, packages, and die complexes all have cities to cross.

He cited Intel's roadmap for promoting system, board, packaging, die development and integration. Content related to advanced packaging includes: System level—reduced movement per unit through improved die and packaging architecture power consumption; board level—integrates optical transmission to continue increasing bandwidth speed and density; packaging level—improves heat dissipation with next-generation thermal interface materials (TIMs), improves power delivery efficiency through Coax MIL, co-packages optics Transmission Components; Composite Die Body—Increase the interconnection bandwidth between dies and develop industry standards for mutual communication (eg UCIe).

It is understood that the UCIe (Universal Chiplet Interconnect Express) advanced packaging common standard led by Intel has won the support of many manufacturers including AMD, Arm, ASE, Google Cloud, Meta, Microsoft, Qualcomm, Samsung, and TSMC. The foundry dies are able to communicate with each other within the package.